1. Field of the Invention
The present invention relates to an evaluation circuit for semiconductor integrated circuits (IC) and, more particularly, to a delay time measuring circuit used for evaluating the operation speed of a high-speed digital circuit operating at extremely high speed.
2. Description of the Related Art
FIG. 1 is a block diagram showing the construction of a conventional evaluation circuit. Conventionally, evaluation for the operation speed of semiconductor integrated circuits is effected by use of an evaluation circuit shown in FIG. 1. That is, a method by using the evaluation circuit is a method for evaluating the delay time, that is, operation speed of an evaluated circuit 1 by supplying first and second clock signals CLK1 and CLK2 from first and second external clock generators 3 and 4. The external clock generators 3 and 4 are independently provided to a flip-flop 2a for latching input data supplied to the evaluated circuit 1 and a flip-flop 2b for latching output data from the evaluated circuit 1 and detecting a phase difference between the two clock signals CLK1 and CLK2 by use of a phase difference detector 5. In this case, reference numerals 7a, 7b and 7d denote input buffers, and 7c denotes an output buffer.
FIG. 2 is a timing chart for illustrating the operation of the evaluation circuit of FIG. 1. As shown in FIG. 2, delay time .tau..sub.d between the clock signals CLK1 and CLK2 is reduced by adjusting the first and second clock generators 3 and 4 so as to change the latch timings of the flip-flops 2a and 2b until output data Dout cannot be detected as a waveform, that is, it fails to be detected. The data latching operation is effected at critical timings. Thus, the minimum permissible phase difference 8 which can permit the evaluated circuit 1 to output correct data can be set. As the phase difference .theta. is set smaller, the operation speed of the evaluated circuit 1 becomes higher. Therefore, the operation speed of the evaluated circuit 1 can be evaluated by detecting the phase difference .theta. by use of the phase difference detector 5.
However, in recent, since the operation speed of ICs is extremely enhanced year by year, errors due to input buffers and input pins of the IC may occur when the conventional method in which two clock signals are independently supplied from the external device as described before. More specifically, since the clock generators 3 and 4 are independently provided, errors due to the individual clock generators 3 and 4 are introduced into the clock signals CLK1 and CLK2. Further, as shown in FIG. 2, an internal clock signal CLK1' input to the flip-flop 2a is delayed by delay time d.sub.1 with respect to the clock signal CLK1 by the presence of the input pin, input buffer 7b and the like. Likewise, an internal clock signal CLK2' input to the flip-flop 2b is delayed by delay time d.sub.2 with respect to the clock signal CLK2. Since the delay times d.sub.1 and d.sub.2 are unstable and d.sub.1 is not equal to d.sub.2, errors occur. Further, the error due to the phase difference detector is added to the above errors. Therefore, with the conventional evaluation method using two types of clock signals which are input from the external device to the chip, the above errors cannot be neglected, particularly, in the case of evaluation of the operation speed of a circuit which operates at extremely high speed, and a problem that desired precision cannot be attained occurs. That is, even if true delay time .tau..sub.d ' can be measured, the true delay time .tau..sub.d ' and apparent delay time .tau..sub.d (phase difference .theta.) of the evaluated circuit 1 do not coincide with each other because of the delay times d.sub.1 .noteq.d.sub.2, etc. and therefore the measurement precision required for evaluation cannot be attained.